Thermal management
for supporting SiC Power Semiconductors

In order to effectively use the limited battery capacity, power loss reduction, miniaturization or weight reduction of power semiconductors equipped on electric-powered automotive vehicles including fully battery electric vehicles (BEVs) or hybrid electric vehicles (HEVs) has been demanded. Such miniaturization or reduction require properties including high voltage, low on-resistance, high-heat resistance, and high-speed switching ability.
Under such circumstances, silicon carbide (SiC) power semiconductors that meet those needs, which were not provided by conventional silicon (Si) power semiconductors, are expected to provide effective and specific solutions for automotive electrification.
Showa Denko Group suggests SiC epitaxial wafer used for automotive vehicles and several material solutions that can be used even in a severe thermal environment exceeding 200℃ to support SiC properties.

Solutions from Showa Denko Group


Power module with a double sided heat spreader

Case type module

SiC epitaxial wafer

Reduces SiC chip defect rate to less than 10%

To improve fuel economy of EV/HEV or miniaturize vehicle drive system power modules, manufacturers are studying introduction of SiC to power semiconductors.
However, the size of chips to be introduced to vehicle drive system power modules, which needs to output high power, is large. For this reason, improvement in surface defects of SiC epitaxial wafer is required in order to increase the yield.
As a solution for this, we suggest that can reduce the defect rate of 1-cm square chip to 10% or less.

* “SiC epitaxial wafer” is a product of Showa Denko.

Our Solution

Reduces SiC chip defect rate to less than 10%

SiC chips can reduce switching loss significantly compared to conventional Si chips, and operate at high temperature of 200℃ or more, thereby enabling improvement in fuel economy of EV/HEV or miniaturization of power modules. However, devices such as vehicle drive system power modules, which need to output high power, require suitable size of chips that match devices. Therefore, improvement in SiC epitaxial wafer quality, which significantly affect the device chip yield, has been a big issue.

Thanks to our advanced epitaxial growth processes, SiC epitaxial wafer <HGE-2G> has a surface defect density, which affects the device initial yield, reduced by 50% or more* compared to the conventional wafer <HGE>Furthermore, conversion efficiency during propagation of basal plane dislocation (BPD : basal plane dislocation)from a substrate, which affects degradation of the device continuity, is increased 10 times or more*, thereby enhancing reliability. As a result, <HGE-2G> can reduce the defect rate of 1-cm square device chip to 10% or less (assuming that defects are caused during epitaxial growth).

* Comparison to our High-Grade Epi <HGE>

Examples of defect improvement

Product features

Reduced surface defect density to 0.1 defects/cm2

Conversion rate during propagation of BPD from a substrate is increased to 10 times or more* compared with that of <HGE>, thereby reducing the surface defect density to approx. 0.1 defects/cm2

Uniform carrier concentration

Thanks to advanced epitaxial growth processes, our product achieves the industry’s narrowest range of the carrier concentration deviation (±8%, Typ value).
*Study by Showa Denko (As of October 2020)

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Sintered Copper Die-bonding Paste

Higher connection reliability compared to high-lead solder or sintered silver. Provides 180 180 W/(m・K) of thermal conductivity.

Die-bonding materials, which are used directly under heat generating semiconductor chips, need to quickly dissipate heat to radiating parts such as thermal interface materials (TIMs) or heat sinks for ensuring semiconductor chip performance.

Although high-lead solder is widely used in die-bonding applications for semiconductor chips, its thermal conductivity is limited to around 30W/(m・K)and the amount of thermal conduction is insufficient. Therefore, a sintered silver paste with high thermal conductivity has been introduced as a substitute. However, it requires high pressure when used in the die-bonding process, which raises problems such as the breaking of semiconductor chips during processing. For this reason, we have developed “sintered copper die-bonding paste,” which has higher thermal conductivity 180W/(m・K)than high-lead solder and allows for die-bonding without thermal compression pressure or with low thermal compression pressure.

* “Sintered Copper Die-bonding Paste” is a product of Showa Denko Materials.

Our Solution

High thermal conductivity(180W/m・K)can resolve problems relating from to high-lead soldering

Conventionally, high-lead solder is widely used in power semiconductors due to its high connection reliability among solder materials. However, its thermal conductivity is lower than those of other component materials, resulting in a challenging bottleneck issue during heat dissipation. In contrast to a general high-lead solder with 30W/(m・K) of thermal conductivity, our sintered copper die-bonding paste has an increased thermal conductivity (180W/(m・K)), to be used as na ideal die-bonding material to overcome the temperature increase in power semiconductors.

Temperature distribution on sample cross-sections
(a) Sample with
sintered copper die-bonding paste
Heat is dissipated from the chip to the board, keeping the chip temperature low.
(b) Sample with
high-lead solder
Heat cannot be dissipated,
increasing the chip temperature.

(Setting items other than material properties)
Electrical power, environment temperature: measured values of samples, air properties: air at normal pressure and 30℃(other physical quantities: fixed values), density: 1.161kg/㎥, thermal conductivity: 2.610 x 10-2 W/(m•K), coefficient of molecular viscosity: 1.840 x 10-5 N•s/㎡, thermal expansion coefficient: 3.333 x 10-3 K-1, conduction, radiation, heat transfer by natural convection, buoyancy, and turbulence were taken into account.

Maintains high connection reliability even when the operating temperature is >175℃

Die-bonding with high-lead solder has the problem that the die-bonding layer suffers fatigue fractures due to the stress caused by the difference in the thermal expansion of parts, resulting in the connection of semiconductor chips not being operating adequately. During the power cycle test (Tj.max= 175℃) it has been proved that our sintered copper die-bonding paste ensures a higher number of cycles than high-lead solder and sintered silver, has good durability, and can maintain the connection reliability of semiconductor chips.

Power Cycle Test Weibull Analysis Results (Tj,max=175℃)

Product Features

High thermal conductivity(180W/(m・K))

The product has a high thermal conductivity 180 W/(m・K), which is five or more times that of high-lead solder 30 W/(m・K) and is most suitable as a die-bonding material for semiconductor chips that are subject to the highest thermal load among power semiconductors.

Two types are available: non-pressure or pressure bonding type

Our lineup of sintered copper die-bonding paste consists of two types: a “non-pressure bonding type” that does not require thermal compression pressure (required gas atmosphere: hydrogen) and a “pressure bonding type” that allows for bonding with 2 MPa or less of thermal compression pressure. Compared to sintered silver paste, which is a die-bonding material also having high thermal conductivity and a thermal compression pressure of 20 MPa, our product allow for bonding with one-tenth of that pressure. Therefore, a contribution to the improvement in the yield rate during semiconductor chip mounting is expected.

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